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| 19-1210; Rev 0; 3/97 KIT ATION EVALU E AILABL AV +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs ______________________________Features o Single +3.3V Supply o 622Mbps Serial to 77Mbps Parallel Conversion o 165mW Power o Synchronization Input for Data Realignment and Reframing o Differential 3.3V PECL Clock and Data Inputs o TTL Data Outputs and Synchronization Input _________________General Description The MAX3680 deserializer is ideal for converting 622Mbps serial data to 8-bit-wide, 77Mbps parallel data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial-clock and data inputs, and delivers TTL clock and data outputs. It also provides a TTL synchronization input that enables data realignment and reframing. The MAX3680 is available in the extended-industrial temperature range (-40C to +85C), in a 28-pin SSOP package. MAX3680 __________________________Applications 622Mbps SDH/SONET Transmission Systems 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross Connects PART MAX3680EAI TEMP. RANGE -40C to +85C PIN-PACKAGE 28 SSOP ________________Ordering Information Pin Configuration appears at end of data sheet. ___________________________________________________________________Typical Operating Circuit VCC = +3.3V VCC PD7 VCC = +3.3V VCC = +3.3V 130 PHOTODIODE 130 SD+ PD5 OVERHEAD TERMINATION MAX3680 PD6 MAX3675 82 LIMITING AMP DATA AND CLOCK RECOVERY 130 82 SDPD4 PREAMP 100 PD3 VCC = +3.3V PD2 130 SCLK+ SCLKPD0 82 82 PCLK SYNC GND PD1 MAX3664 THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680 ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC ...........................................................................-0.5V to 5V PECL Inputs (SD+/-, SCLK+/-) .................-0.5V to (VCC + 0.5V) TTL Input (SYNC) .....................................-0.5V to (VCC + 0.5V) TTL Outputs (PCLK, PD_).........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) SSOP (derate 9.52mW/C above +85C) ......................619mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current PECL INPUTS (SD+/-, SCLK+/-) Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage VIH VIL IIH IIL VIH VIL IIH IIL VOH VOL VIN = VIH(MAX) VIN = VIL(MAX) Output sourcing = 400A Output sinking = 400A -10 -10 2.4 0 VIN = VIH(MAX) VIN = VIL(MAX) VCC - 1.16 VCC - 1.81 -10 -10 2.0 0.8 10 10 VCC 0.44 VCC - 0.88 VCC - 1.48 10 10 V V A A V V A A V V SYMBOL ICC CONDITIONS TTL outputs = high MIN 25 TYP 50 MAX 90 UNITS mA TTL INPUT AND OUTPUTS (SYNC, PCLK, PD_) AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Maximum Serial Clock Frequency Serial Data Setup Time Serial Data Hold Time Parallel Clock to Data Output Delay SYMBOL fSCLK tSU tH tCLK-Q VCC = 3.3V, CL = 18pF CONDITIONS MIN 622 800 50 -200 500 1300 TYP MAX UNITS MHz ps ps ps Note 1: AC characteristics guaranteed by design and characterization. 2 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs __________________________________________Typical Operating Characteristics (VCC = +3.0V to +3.6V, unless otherwise noted.) MAX3680 MAXIMUM SERIAL-CLOCK FREQUENCY vs. TEMPERATURE MAX3680-01 SERIAL DATA-SETUP TIME vs. TEMPERATURE MAX3680-02 1.3 SERIAL CLOCK FREQUENCY (GHz) 1.2 400 SERIAL DATA-SETUP TIME (ps) 360 1.1 1.0 320 280 0.9 240 0.8 -50 -25 0 25 50 75 100 TEMPERATURE (C) 200 -50 -25 0 25 50 75 100 TEMPERATURE (C) SERIAL DATA-HOLD TIME vs. TEMPERATURE MAX3680-03 SUPPLY CURRENT vs. TEMPERATURE MAX3680-04 400 SERIAL DATA-HOLD TIME (ps) 340 70 60 SUPPLY CURRENT (mA) 50 40 30 20 10 VCC = 3.0V VCC = 3.3V VCC = 3.6V 280 220 160 100 -50 -25 0 25 50 75 100 TEMPERATURE (C) 0 -50 -25 0 25 50 75 100 TEMPERATURE (C) _______________________________________________________________________________________ 3 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680 ______________________________________________________________Pin Description PIN 1, 2, 5, 8, 14, 18, 25 3 4 6 7 9, 11, 12, 16, 20, 23, 27 10 13 15, 17, 19, 21, 22, 24, 26, 28 NAME VCC SD+ SDSCLK+ SCLKGND SYNC PCLK PD0-PD7 +3.3V Supply Voltage Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal's positive transition. Inverting PECL Serial Data Input. Data is clocked on the SCLK signal's positive transition. Noninverting PECL Serial Clock Input Inverting PECL Serial Clock Input Ground TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data alignment by dropping one bit in the serial input data stream. TTL Parallel Clock Output TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment. FUNCTION _______________Detailed Description The MAX3680 deserializer uses an 8-bit shift register, 8-bit parallel output register, 3-bit counter, PECL input buffers, and TTL input/output buffers to convert 622Mbps serial data to 8-bit-wide, 77Mbps parallel data (Figure 1). The input shift register continuously clocks incoming data on the positive transition of the serial clock (SCLK) input signal. The 3-bit counter generates a parallel output clock (PCLK) by dividing down the serial clock frequency. The PCLK signal is used to clock the parallel output register. During normal operation, the counter divides the SCLK frequency by eight, causing the output register to latch every eight bits of incoming serial data. The synchronization input (SYNC) is used for data realignment and reframing. When the SYNC signal is pulsed high for at least two SCLK cycles, PCLK is delayed by one SCLK cycle, causing the first incoming bit of the serial input data stream to be dropped. This realignment is guaranteed to occur within two PCLK cycles of the SYNC rising edge. See Figure 2 for the functional timing diagrams and Figure 3 for the timing parameters diagram. TTL SD+ SDSCLK+ SCLKPECL TTL 8-BIT PARALLEL OUTPUT REGISTER PECL 8-BIT SHIFT REGISTER TTL PD7 PD6 TTL PD5 PD4 TTL PD3 TTL PD2 MAX3680 TTL PD1 TTL 3-BIT COUNTER PD0 SYNC TTL TTL PCLK Figure 1. Functional Diagram 4 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680 SCLK* SD* D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 PCLK PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 D8D7D6D5D4D3D2D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 2a. Functional Timing Diagram--Normal Operation _______________________________________________________________________________________ 5 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680 SCLK* SD* D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 SYNC PCLK PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 D8D7D6D5D4D3D2D1- D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 2b. Functional Timing Diagram--SYNC Operation tSCLK = 1 / fSCLK SCLK* tSU SD* tH PCLK tCLK-Q PD0-PD7 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 3. Timing Parameters 6 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs PECL Inputs The serial data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-) require 50 termination to (VCC - 2V) when interfacing with a PECL source (see Alternative PECL Input Termination). THEVENIN-EQUIVALENT TERMINATION +3.3V 130 ZO = 50 130 MAX3680 __________Applications Information Alternative PECL Input Termination Figure 4 shows alternative PECL input-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, such as when interfacing with an ECL-output device, use the ECL AC-coupling termination. MAX3680 PECL INPUTS ZO = 50 82 82 Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the MAX3680 data inputs. ECL AC-COUPLING TERMINATION +3.3V 1.6k ZO = 50 1.6k MAX3680 50 PECL INPUTS __________________Pin Configuration TOP VIEW VCC 1 VCC 2 SD+ 3 SD- 4 VCC 5 SCLK+ 6 SCLK- 7 VCC 8 GND 9 SYNC 10 GND 11 GND 12 PCLK 13 VCC 14 28 PD7 27 GND 26 PD6 25 VCC ZO = 50 -2V 50 2.7k -2V 2.7k Figure 4. Alternative PECL Input Termination MAX3680 24 PD5 23 GND 22 PD4 21 PD3 20 GND 19 PD2 18 VCC 17 PD1 16 GND 15 PD0 ___________________Chip Information TRANSISTOR COUNT: 1346 SSOP _______________________________________________________________________________________ 7 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680 ________________________________________________________Package Information SSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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